Testing of very large scale integration (VLSI) designs becomes more common with the growth of the complexity of such designs. Testing should be very accurate to reduce the number of non-detected faults. Testing should also be fast and inexpensive in terms of hardware and software overhead. An especially important task is the testing of memories. In the synthesis of VLSI designs, memories in the designs have a much higher defect density than other logic and thus involve additional and comprehensive testing. To reduce the size of a memory, gates and wires are typically placed very densely on a semiconductor wafer. Dense placement often results in a significantly higher ratio of faults (i.e., up to 4 times higher) in these areas.
Fortunately, memories are very regular structures, so testing can be done on-chip, based on data sequences generated by relatively small processors. One conventional solution is to test memories using a built-in memory test (MT) controller that performs corresponding MT schemes. During a test, the MT controller sends input data, usually to a memory collar, along with expected memory output data in order to perform a comparison with the actual memory output data at each time a comparison is to be performed. The expected memory output data can be computed/predicted at the test process level (rather than in the MT controller). However, computation/prediction of the expected memory output data at the test process level can be memory dependent. In the case of a 2-port memory, when reading through port B, data stored in the memory at an address ADRB can appear to be adjusted to an address ADRA associated with port A. In this case, the adjusted addresses depend on the memory column multiplexing and how the address ADRB is generated. Such an implementation can be cumbersome because the MT controller needs to provide a large amount of test specific information that can require additional wires between the MT controller and the memory collar.
It would be desirable to implement a system and/or method that may be used to test memories of different sizes and types without being cumbersome or requiring additional wires between the MT controller and the memory collar.